Global Standards for the Microelectronics Industry
Standards & Documents Search
Title | Document # | Date |
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TS511X, TS521X Serial Bus Thermal Sensor Device Standard |
JESD302-1A | Aug 2023 |
This standard defines the specifications of interface parameters, signaling protocols, and features for fifth generation Temperature Sensor (TS5) as used for memory module applications. These device operate on I2C and I3C two-wire serial bus interface. The designation TS521X and TS511X refers to the device specified by this document. Committee(s):JC-40.1 Free download.Registrationorloginrequired. |
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JOINT JEDEC/ESDA STANDARD FOR ELECTROSTATIC DISCHARGE SENSITIVITY TEST - HUMAN BODY MODEL (HBM) - COMPONENT LEVEL |
JS-001-2023 | Jul 2023 |
这对于testin标准建立了程序g, evaluating, and classifying components and microcircuits according to their susceptibility (sensitivity) to damage or degradation by exposure to a defined human body model (HBM) electrostatic discharge (ESD). The purpose (objective) of this standard is to establish a test method that will replicate HBM failures and provide reliable, repeatable HBM ESD test results from tester to tester, regardless of component type. Repeatable data will allow accurate classifications and comparisons of HBM ESD sensitivity levels. NOTE Data previously generated with testers meeting all waveform criteria of ANSI/ESD STM5.1-2007 or JESD22A-114F shall be considered valid test data. Also availableJTR-001-01-12: User Guide of ANSI/ESDA/JEDEC JS-001, Human Body Model Testing of Integrated Circuits Free download.Registrationorloginrequired. |
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Registration - Plastic Dual Upper to Bottom, 1.8 mm x 1.00 mm Pitch Connector (CMT) |
SO-032A | Jul 2023 |
Designator: PDUtBXC-H...Item: 11.14-215, AccessSTP File for SO-032ACross Reference: N/A Committee(s):JC-11.14 Free download.Registrationorloginrequired. |
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JC-42.6 MANUFACTURER IDENTIFICATION (ID) CODE FOR LOW POWER MEMORIES |
JEP166E | Jul 2023 |
This document defines the JC-42.6 Manufacturer ID. This document covers Manufacturer ID Codes for the following technologies: LPDDR (JESD209), LPDDR2 (JESD209-2), LPDDR3 (JESD209-3), LPDDR4 (JESD209-4), Wide-IO (JESD229), and Wide-IO2 (JESD229-2). The purpose of this document is to define the Manufacturer ID for these devices. Item No. 1725.03C. See Annex for additions/changes. To make a request for an ID code://www.ljosalfur.com/id-codes-low-power-memories Committee(s):JC-42.6 Free download.Registrationorloginrequired. |
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LOW POWER DOUBLE DATA RATE (LPDDR) 5/5X |
JESD209-5C | Jul 2023 |
This document defines the LPDDR5/LPDDR5X standard, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this specification is to define the minimum set of requirements for a JEDEC compliant x16 one channel SDRAM device and x8 one channel SDRAM device. LPDDR5/LPDDR5X device density ranges from 2 Gb through 32 Gb. This document was created using aspects of the following standards: DDR2 (JESD79-2), DDR3 (JESD79-3), DDR4 (JESD79-4), LPDDR (JESD209), LPDDR2 (JESD209-2), LPDDR3 (JESD209-3), and LPDDR4 (JESD209-4). Available for purchase:$459.00 Add to Cart Paying JEDEC Members mayloginfor free access. |
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ESDA/JEDEC JOINT STANDARD FOR ELECTROSTATIC DISCHARGE SENSITIVITY TESTING – CHARGED DEVICE MODEL (CDM) – DEVICE LEVEL |
JS-002-2022 | Jun 2023 |
这对于testin标准建立了程序g, evaluating, and classifying devices and microcircuits according to their susceptibility (sensitivity) to damage or degradation by exposure to a defined field-induced charged device model (CDM) electrostatic discharge (ESD). All packaged semiconductor devices, thin film circuits, surface acoustic wave (SAW) devices, opto-electronic devices, hybrid integrated circuits (HICs), and multi-chip modules (MCMs) containing any of these devices are to be evaluated according to this standard. This test method combines the main features of JEDEC JESD22-C101 and ANSI/ESD S5.3.1. Free download.Registrationorloginrequired. |
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GUIDELINE FOR OBTAINING AND ACCEPTING MATERIAL FOR USE IN HYBRID/MCM PRODUCTSStatus: ReaffirmedMay 2023 |
JEP142 | May 2023 |
This document provides guidance regarding design considerations, material assessment techniques, and recommendations for material acceptance prior to use in Hybrid/MCM Products. As part of the risk assessment process, both technical requirements and cost should be carefully considered with regard to testing/evaluating the elements of a hybrid microcircuit or Multi-chip Module (MCM) prior to material release for assembly. The intent of this document is to highlight various options that are available to the Hybrid / MCM manufacturer and provide associated guidance, not to impose a specific set of tests. Free download.Registrationorloginrequired. |
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Graphics Double Data Rate (GDDR6) SGRAM Standard |
JESD250D | May 2023 |
This document defines the Graphics Double Data Rate 6 (GDDR6) Synchronous Graphics Random Access Memory (SGRAM) specification, including features, functionality, package, and pin assignments. The purpose of this Standard is to define the minimum set of requirements for 8 Gb through 16 Gb x16 dual channel GDDR6 SGRAM devices. System designs based on the required aspects of this standard will be supported by all GDDR6 SGRAM vendors providing compatible devices. Some aspects of the GDDR6 standard such as AC timings and capacitance values were not standardized. Some features are optional and therefore may vary among vendors. In all cases, vendor data sheets should be consulted for specifics. This document was created based on some aspects of the GDDR5 Standard (JESD212). Committee(s):jc - 42.3C Free download.Registrationorloginrequired. |
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Statistical Process Control Systems |
JESD557D | May 2023 |
This standard specifies the general requirements of a statistical process control (SPC) system. This is a revision of JESD557C. Committee(s):JC-14 Free download.Registrationorloginrequired. |
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Guidelines for Particle Impact Noise Detection (PIND) Testing, Operator Training, and Certification |
JEP114A | May 2023 |
This publication is a guideline to test facilities in their efforts to establish and maintain consistent particle impact noise detection (PIND) testing. Free download.Registrationorloginrequired. |
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Guidelines for Supplier Performance Rating |
JEP146B | May 2023 |
This publication establishes guidelines and provides examples by which customers can measure their suppliers based on mutually agreed upon objective criteria. Free download.Registrationorloginrequired. |
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NAND Flash Interface Interoperability |
JESD230F.01 | May 2023 |
This standard was jointly developed by JEDEC and the Open NAND Flash Interface Workgroup, hereafter referred to as ONFI. This standard defines a standard NAND flash device interface interoperability standard that provides means for system be designed that can support Asynchronous SDR, Synchronous DDR and Toggle DDR NAND flash devices that are interoperable between JEDEC and ONFI member implementations. Committee(s):JC-42.4 Free download.Registrationorloginrequired. |
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HYBRIDS/MCM |
JESD93A | May 2023 |
This specification establishes the general requirements for hybrid microcircuits, RF/microwave hybrid microcircuits and MCMs (hereafter referred to as devices). Detailed performance requirements for a specific device are specified in the applicable device acquisition document. In the event of a conflict between this document and the device acquisition document, the device acquisition document will take precedence. Committee(s):JC-14.3 Free download.Registrationorloginrequired. |
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DDR5 Clock Driver Definition (DDR5CK01) |
JESD82-531 | May 2023 |
本文档定义了标准规格的DC interface parameters, switching parameters, and test loading for definition of the DDR5 Clock Driver (CKD) for re-driving the DCK for CUDIMM, CSODIMM and CAMM applications. The DDR5CK01 Device ID is DID = 0x0531. (5 = DDR5, 3= Clock Driver, 1= rev 01). Committee(s):JC-40.4 Free download.Registrationorloginrequired. |
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SPD5118 HUB and SERIAL PRESENCE DETECT DEVICE STANDARDRelease Number: Version 1.5.1 |
JESD300-5B.01 | May 2023 |
This standard defines the specifications of interface parameters, signaling protocols, and features for DDR5 Serial Presence Detect EEPROM with Hub function (SPD5 Hub) and integrated Temperature Sensor (TS) as used for memory module applications. The Hub feature allows isolation of a local bus from a Controller host bus. The designation SPD5118 or generic term SPD5 Hub refers to the devices specified by this standard. Committee(s):JC-40.1 Free download.Registrationorloginrequired. |
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STANDARD MANUFACTURERS IDENTIFICATION CODENOTE: JEP106U was in error starting with bank two an additional continuation code was added, JEP106U should be discarded. |
JEP106BG | May 2023 |
The manufacturers identification code is defined by one or more 8 bit fields, each consisting of 7 data bits plus 1 odd parity bit. The manufacturers identification code is assigned, maintained and updated by the JEDEC Office. The intent of this identification code is that it may be used whenever a digital field is required, e.g., hardware, software, documentation, etc. To make a request for an ID Code please go to//www.ljosalfur.com/standards-documents/id-codes-order-form Free download.Registrationorloginrequired. |
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REGISTRATION - 288 PIN DDR5 DIMM SMT, 0.85 MM PITCH SOCKET OUTLINE |
SO-023D | May 2023 |
Designator: PDXC-LO288-I0p85-R162p0x6p5Z21p3-N5p20S3p1Z0p2Item: 11.14-216, AccessSTP Files for SO-023CCross Reference: MO-329, GS-010C Patents(): CN 202759077 U Committee(s):JC-11.14 Free download.Registrationorloginrequired. |
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DDR4 NVDIMM-N Design Standard |
JESD248A.01 | Apr 2023 |
术语更新。 This standard defines the electrical and mechanical requirements for 288-pin, 1.2 Volt (VDD), Double Data Rate, Synchronous SDRAM Non-Volatile Dual In-Line Memory Modules with NAND Flash backup (DDR4 NVDIMM-N). A DDR4 NVDIMM-N is a Hybrid Memory Module with a DDR4 DIMM interface consisting of DRAM that is made non-volatile through the use of NAND Flash. Committee(s):JC-45.6 Available for purchase:$123.36 Add to Cart Paying JEDEC Members mayloginfor free access. |
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STANDARD TEST STRUCTURE FOR RELIABILITY ASSESSMENT OF AlCu METALLIZATIONS WITH BARRIER MATERIALSStatus: Reaffirmed04/17/2023 |
JESD87 | Apr 2023 |
This document describes design of test structures needed to assess the reliability of aluminum-copper, refractory metal barrier interconnect systems. This includes any metal interconnect system where a refractory metal barrier or other barrier material prevents the flow of aluminum and/or copper metal ions from moving between interconnect layers. This document is not intended to show design of test structures to assess aluminum or aluminum-copper alloy systems, without barriers to Al and Cu ion movement, nor for Cu only metal systems. Some total interconnect systems might not include barrier materials on all metal layers. The structures in this standard are designed for cases where a barrier material separates two Al or Al alloy metal layers. The purpose of this document is to describe the design of test structures needed to assess electromigration (EM) and stress-induced-void (SIV) reliability of AlCu barrier metal systems. Free download.Registrationorloginrequired. |
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STANDARD METHOD FOR CALCULATING THE ELECTROMIGRATION MODEL PARAMETERS FOR CURRENT DENSITY AND TEMPERATURE:Status: Reaffirmed4/17/23 |
JESD63 | Apr 2023 |
This method provides procedures to calculate sample estimates and their confidence intervals for the electromigration model parameters of current density and temperature. The model parameter for current density is the exponent (n) to which the current density is raised in Black's equation. The parameter for temperature is the activation energy for the electromigration failure process. Committee(s):JC-14.2 Free download.Registrationorloginrequired. |
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Registration - Shipping and Handling Tray for M.2 Type 2280 SSD Microelectronic Assembly |
CO-038A | Apr 2023 |
Designator: N/A Committee(s):JC-11.5 Free download.Registrationorloginrequired. |
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Registration - Shipping and Handling Tray for M.2 Type 2230 Microelectronic Assembly |
CO-039A | Apr 2023 |
Designator: N/A Committee(s):JC-11.5 Free download.Registrationorloginrequired. |
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PMIC50x0 Power Management IC Standard |
JESD301-1A.02 Rev. 1.8.5 | Apr 2023 |
This standard defines the specifications of interface parameters, signaling protocols, and features for PMIC device asused for memory module applications. The designation PMIC5000, PMIC5010 refers to the device specified by this document. The purpose is to provide a standard for the PMIC5000, PMIC5010 device for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. Committee(s):JC-40.1 Free download.Registrationorloginrequired. |
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Temperature Cycling |
JESD22-A104F.01 | Apr 2023 |
This standard applies to single-, dual- and triple-chamber temperature cycling in an air or other gaseous medium and covers component and solder interconnection testing. Committee(s):JC-14.1 Free download.Registrationorloginrequired. |
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Registration - Plastic Quad Flat Package, Gull Wing and J-Lead, 0.65 MM Pitch |
MO-355A | Apr 2023 |
Designator: PQFP-E#_I0p65-R... Committee(s):JC-11.11 Free download.Registrationorloginrequired. |
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Graphics Double Data (GDDR4) SGRAM StandardRelease Number: 16 |
SDRAM3.11.5.8 R16.01 | Mar 2023 |
Item 1600.41, Terminology Update This document defines the Graphics Double Data Rate 4 (GDDR4) Synchronous Graphics RandomAccess Memory (SGRAM) standard, including features, functionality, package, and pin assignments. This scope may be expanded in future to also include other higher density devices. Committee(s):jc - 42.3 Free download.Registrationorloginrequired. |
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Multichip Packages (MCP) and Discrete e•MMC, e•2MMC, and UFSRelease Number: 32 |
MCP3.12.1 | Mar 2023 |
Item 140.07B. This section provides electrical interface items related to Multi-Chip Packages (MCP) and Stacked-Chip Scale Packages (SCSP) of mixed memory technologies including Flash (NOR and NAND), SRAM, PSRAM, LPDRAM, USF, etc. These items include die-on-die stacking within a single encapsulated package, package-on-package or module-in-package technologies, etc. The Section also contains Silicon Pad Sequence information for the various memory technologies to aid in the design and electrical optimization of the memory sub-system or complete memory stacked solution. Committee(s):JC-64.2 Free download.Registrationorloginrequired. |
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Definition of the SSTUB32869 Registered Buffer with Parity for DDR2 RDIMM Applications |
JESD82-27.01 | Mar 2023 |
术语更新。This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the SSTUB32869 registered buffer with parity for driving heavy load on high density DDR2 RDIMM applications. A typical application would be a 36 SDRAM planar DIMM. Committee(s):JC-40 Free download.Registrationorloginrequired. |
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Fully Buffered DIMM Design for Test, Design for Validation (DFx) |
JESD82-28A.01 | Mar 2023 |
术语更新。This FBDIMM DFx standard covers Design for Test, Design for Manufacturing, and Design for Validation (“DFx”) requirements and implementation guidelines for Fully Buffered DIMM technology. Patents(): There are known patent issues that are common to all FBDIMM related specifications. See document for link to FBDIMM Patents. Free download.Registrationorloginrequired. |
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RADIO FRONT END - BASEBAND DIGITAL PARALLEL (RBDP) INTERFACE |
JESD207.01 | Mar 2023 |
术语更新。This document establishes an interface standard for the data path and control plane interface functions for an RFIC component and/or a BBIC component. Committee(s):JC-61 Free download.Registrationorloginrequired. |
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GRAPHICS DOUBLE DATA RATE (GDDR5X) SGRAM STANDARD |
JESD232A.01 | Mar 2023 |
术语更新。 This standard defines the Graphics Double Data This standard defines the GDDR5X SGRAM memory standard, including features, device operation, electrical characteristics, timings, signal pin assignments, and package Committee(s):jc - 42.3,jc - 42.3C Free download.Registrationorloginrequired. |
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SILICON RECTIFIER DIODES: |
JESD282B.02 | Mar 2023 |
术语更新。This legacy document is a comprehensive users’ guide for silicon rectifier diode applications. Committee(s):JC-22.2 Free download.Registrationorloginrequired. |
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DEFINITION OF THE SSTVN16859 2.5-2.6 V 13-BIT TO 26-BIT SSTL_2 REGISTERED BUFFER FOR PC1600, PC2100, PC2700 AND PC3200 DDR DIMM APPLICATIONS |
JESD82-13A.01 | Mar 2023 |
术语更新。Definition of the SSTVN16859 2.5-2.6 V 13-Bit to 26-Bit SSTL_2 Registered Buffer for PC1600, PC2100, PC2700, and PC3200 DDR DIMM Applications Committee(s):JC-40 Free download.Registrationorloginrequired. |
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JEDEC Legal Guidelines |
JM5.01 | Mar 2023 |
术语更新。This document sets forth the best judgment of the standards of conduct and legal restraints that must be observed to protect against violations of the law. Free download.Registrationorloginrequired. |
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COMPACT THERMAL MODEL OVERVIEW |
JESD15-1.01 | Mar 2023 |
术语更新。这个文档应该使用conjunction with the parent document, and is intended to function as an overview to support the effective use of Compact Thermal Model (CTM) methodologies as specified in the companion methods documents. Free download.Registrationorloginrequired. |
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RADIO FRONT END - BASEBAND (RF-BB) INTERFACE |
JESD96A.01 | Mar 2023 |
术语更新。This standard establishes the requirements for an interface between Radio Front End (RF) and Baseband (BB) integrated circuits (IC). Committee(s):JC-61 Free download.Registrationorloginrequired. |
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Compute Express Link (CXL™) Memory Module Base Standard |
JESD317 | Mar 2023 |
This standard defines the specifications of interface parameters, signaling protocols, environmental requirements, packaging, and other features as reference for specific target implementations of CXL™-attached memory modules.The purpose is to provide certain reference base targets for CXL™-attached memory modules to enable system design simplification, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. Committee(s):JC-45 Free download.Registrationorloginrequired. |
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Registration - Plastic Bottom Grid Array, 0.80 MM Pitch, Rectangular Family Package |
MO-210R | Mar 2023 |
Designator: PBGA-B#[#]_I0p... Patents(): May apply: Micron: 6,048,753. Tessera: 5,950,304; and 6,133,627 Committee(s):JC-11.11 Free download.Registrationorloginrequired. |
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Registration - Plastic Bottom Grid Array Ball, 0.40 MM Pitch Rectangular Family Package |
MO-352A.01 | Mar 2023 |
Designator: PBGA-B#[#}_I0p4... Committee(s):JC-11.11 Free download.Registrationorloginrequired. |
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DDR5 DIMM Labels |
JESD401-5A | Mar 2023 |
This standard for labels applies to all DDR5 memory modules to fully describe the key attributes of the module. The label can be in the form of a stick-on label, silk screened onto the assembly, or marked using an alternate customer-readable format, Item 2268.02C Committee(s):JC-45 Free download.Registrationorloginrequired. |