Automotive Electronics Forum

With rapid transition towards autonomy and electrification in automobiles, importance of high-performance and robustness in computing systems in vehicles are growing more than ever before. In order to achieve such goals, four key factors “Smartness, Intelligence, Safety, and Security” need to be considered. And, memory and Storage constitutes an important part of computing systems to satisfy such needs. First for smartness, such as in smart cockpits, high-performance memory and high-capacity storage are required. Second for intelligence, such as in self-driving and ADAS, high-bandwidth low-power memory is essential. Third for safety, high fault-tolerant memory and storage having high RAS capability with auto-grade quality are needed. Finally for Security against external intrusion, adoption of secure features in memory and storage would be necessary. In this presentation, we explain how each of these goals can be achieved using memory and storage tailored to such individual needs.

Automotive-safe semiconductors have been in vehicles for a long time, and were previously used for important but lower-level functions like braking, drivetrain and cruise control. The latest chips being designed for Advanced Driver Awareness Systems (ADAS) and Autonomous Driving (AD) applications are very different, requiring a large amount of compute power and memory bandwidth, while remaining automotive safe. This presentation will discuss the fundamentals of creating an automotive safe chip, from aligning the organization to operate in a functionally safe way, to reasonable targets for ISO26262 and AEC Q100 automotive standards, and achieving success at functional safety audit.

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A modern Electric Vehicle (EV) is essentially a computer on wheels with a variety of complex compute domains that have a set of constraints unique to each domain. This talk looks explores the basic functionality of these compute domains and how the attributes of the memory subsystems vary with the workloads.

Next-generation automotive ecosystems present a difficult set of requirements for consideration by chipset developers. Dramatically higher computing requirements, operation at elevated temperatures and the migration to advanced process nodes all need evaluation. This session discusses these automotive ecosystem requirements and the effort to place non-volatile memory on the widely adopted JEDEC LPDDR interface to address this challenging environment

有计算需求ADA指数上升S for Automoted driving as well as ECU Consolidation in MCU space for new Zonal EE architecture, whic drives new generation of MCU and processors in Automotive space. This poses new requirements from memory esp DRAM technolgoy as well as flash (NAND/NOR). The talk provides trends of technology for various ECU and density neeeds. The automotive market poses additional challenges in terms of cost, thermal and functional safety. The talk provides use-case example for each challenges and typical solution deployed. The 3 use-case namely Themal challenges with LPDDR4, performance challengeng eXecuteInPlace (XIP) for NOR flash and System challenges with serial NAND are discussed in detail to explain Automotive care-abouts wrt various memories technologies.

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Starting from an introduction of Micron 30 years commitment to the automotive market and major milestones, the presentation will go through the Micron Foundations of Quality and the evolution from internal combustion engine to the electrical vehicles mission profiles and usage models.

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数据流量的激增使得数据中心/ cloud computing workloads demand to grow exponentially. The data center processors are seeing mixture of file sizes, diversified data types and new algorithms for varying processing requirements. Adding to the challenge is the workload evolution, with cloud-based ML/AI (Hardware Machine Learning & Artificial Intelligence) being the first and foremost. The processing speed and bandwidth demand increase the data center burden. Example workloads targeted for acceleration are data analytics, networking application and cybersecurity. Adaptable system accelerator, such as implemented with FPGA, have bridged the computational gap by providing heterogenous acceleration to offload the burden. However, the new data path, such as in ML, is fundamentally different from the traditional CPU data path flow. This presentation will highlight the diverse applications of programmable system and contrast the different system memory (e.g., DDR5) requirement to traditional CPU system requirement. The discussion will stress on the balance among system cost, bandwidth and memory density requirement going forward.

This presentation covers architecture evolution for In-Vehicle Infotainment (IVI) and Advanced Driver Assist Systems (ADAS) systems that the Automotive Industry is undergoing to deliver the next level of experiences to drivers and passengers. It covers the Market trends driving this change and also focuses on technology enabling it.

The transition from the legacy Internal Combustion Engine (ICE) to the contemporary Battery Electric Vehicle (BEV) automotive platforms resulted in the development of automotive electronic systems not previously employed in ICE applications. Along with proliferation of control systems supporting various functions related to sensing and connectivity resulted in an exponential growth of electronic content in contemporary automotive platforms that can be subjected to use conditions that can differ from the legacy use conditions originally developed for ICE platforms. Years of collective industry ICE platform knowledge enabled the standardization of the qualification procedures applied to automotive semiconductor products; facilitating an efficient and cost effective semiconductor product development and qualification process supporting the deployment of (non-ASIC) catalog products destined for the general automotive market. Today, the multiple iterations of yet to be standardized contemporary use conditions provided by multiple end-users for similar end applications are causing inefficiencies in the product development and qualification process. The presentation will speak to the concept of Standardized Mission Profiles as applied to some of the automotive applications seen in contemporary automotive platforms.

AS THE AUTOMOTIVE INDUSTRY transitions manufacturing from the cars with combustion engines to electric vehicles (EV), a dramatic increase in the requested power-on hours (POH) required for semiconductor ICs is also occurring.

The legacy reliability approach of using the Arrhenius equation and performing High Temperature Operating Life (HTOL) stress testing to match extended POH (> 20,000 POH) can give a false assurance of reliability.

A more analytic approach is to assess the application-specific use profile against the intrinsic reliability models of semiconductor wear-out mechanisms. This method is called the ZVEI Robustness Validation (RV) process and is described in appendix 7 of AEC-Q100 specification.