Global Standards for the Microelectronics Industry
Standards & Documents Search
Title | Document # | Date |
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FOUNDRY PROCESS QUALIFICATION GUIDELINES - BACKEND OF LIFE (Wafer Fabrication Manufacturing Sites) |
JEP001-1A | Sep 2018 |
This document describes backend-level test and data methods for the qualification of semiconductor technologies. It does not give pass or fail values or recommend specific test equipment, test structures or test algorithms. Wherever possible, it references applicable JEDEC such as JESD47 or other widely accepted standards for requirements documentation. Committee(s):JC-14.2 Free download.Registrationorloginrequired. |
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GUIDELINE FOR OBTAINING AND ACCEPTING MATERIAL FOR USE IN HYBRID/MCM PRODUCTSStatus: ReaffirmedMay 2023 |
JEP142 | May 2023 |
This document provides guidance regarding design considerations, material assessment techniques, and recommendations for material acceptance prior to use in Hybrid/MCM Products. As part of the risk assessment process, both technical requirements and cost should be carefully considered with regard to testing/evaluating the elements of a hybrid microcircuit or Multi-chip Module (MCM) prior to material release for assembly. The intent of this document is to highlight various options that are available to the Hybrid / MCM manufacturer and provide associated guidance, not to impose a specific set of tests. Free download.Registrationorloginrequired. |
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GUIDELINE FOR CHARACTERIZING SOLDER BUMP ELECTROMIGRATION UNDER CONSTANT CURRENT AND TEMPERATURE STRESSStatus: ReaffirmedJune 2011 |
JEP154 | Jan 2008 |
This document describes a method to test the electromigration (EM) susceptibility of solder bumps, including other types of bumps, such as solder capped copper pillars, used in flip-chip packages. The method is valid for Sn/Pb eutectic, high Pb, and Pb-free solder bumps. The document discusses the advantages and concerns associated with EM testing, as well as options for data analysis. Free download.Registrationorloginrequired. |
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CHIP-PACKAGE INTERACTION UNDERSTANDING, IDENTIFICATION AND EVALUATION |
JEP156A | Mar 2018 |
This publication references a set of frequently recommended and accepted JEDEC reliability stress tests. These tests are used for qualifying new and modified technology/ process/ product families, as well as individual solid state surface-mount products. Free download.Registrationorloginrequired. |
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GUIDELINES FOR VISUAL INSPECTION AND CONTROL OF FLIP CHIP TYPE COMPONENTS (FCxGA)Status: ReaffirmedMay 2018 |
JEP170 | Jan 2013 |
This publication provides description of defects observed in FCxGA components that can adversely impact end-user products and/or applications. It will also provide illustration on other defects that may be considered visual nonconformities since they should be less disruptive of quality or reliability to customer products. Finally, it will depict a method for visual inspection that can be utilized to identify these defects or visual nonconformities and guidance for disposition. Official criteria for product acceptance should be in actual product drawings and specifications. Committee(s):JC-14.1 Free download.Registrationorloginrequired. |
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固体产品登记列表(订单TYPE ADMINISTRATION OFFICE)Status: ReaffirmedNovember 2002 |
JEP64 | Jan 1986 |
This publication includes addenda from 1976 to August 1986. The purpose of this list is to determine release numbers (file numbers) for JEDEC Type Designations. (See page 6 for more information.) Committee(s):JCJEDC |
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STRESS-TEST-DRIVEN QUALIFICATION OF AND FAILURE MECHANISMS ASSOCIATED WITH ASSEMBLED SOLID STATE SURFACE-MOUNT COMPONENTS |
JEP150.01 | Jun 2013 |
This publication contains a set of frequently recommended and accepted JEDEC reliability stress tests. These tests are used for qualifying new and modified technology/ process/ product families, as well as individual solid state surface-mount products, in particular leadless chip carriers, ball grid array (BGA) packages, direct chip attach die and packages with exposed pads that are attached to the PWB for thermal considerations. Assembly level testing may not be a prerequisite for device qualification; however, if the effect of assembly conditions on the component is not known, there could be reliability concerns for that component that are not evident in component level testing. As such, it is recommended that assembly level testing be performed to determine if there are any adverse effects on that component due to its assembly to a PWB. Free download.Registrationorloginrequired. |
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CHARACTERIZATION AND MONITORING OF THERMAL STRESS TEST OVEN TEMPERATURESStatus: ReaffirmedSeptember 2019 |
JEP153A | Mar 2014 |
This document provides an industry standard method for characterization and monitoring thermal stress test oven temperatures. The procedures described in this document should be used to insure thermal stress test conditions are being achieved and maintained during various test procedures. Free download.Registrationorloginrequired. |
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A PROCEDURE FOR EXECUTING SWEAT:Status: ReaffirmedOctober 2012, September 2018 |
JEP119A | Aug 2003 |
This document describes an algorithm for performing the Standard Wafer Level Electromigration Accelerated Test (SWEAT) method with computer controlled instrumentation. The algorithm requires a separate iterative technique (not provided) to calculate the force current for a given target time to failure. This document does not specify what test structure to use with this procedure. However, users of this algorithm report its effectiveness on both straight-lines and via-terminated test structures. Some test-structures design features are provided in JESD87 and in ASTM 1259M - 96. Committee(s):JC-14.2 Free download.Registrationorloginrequired. |
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GUIDELINE FOR CONSTANT TEMPERATURE AGING TO CHARACTERIZE ALUMINUM INTERCONNECT METALLIZATIONS FOR STRESS-INDUCED VOIDING:Status: ReaffirmedOctober 2012 |
JEP139 | Dec 2000 |
This document describes a constant temperature (isothermal) aging method for testing aluminum (Al) metallization test structures on microelectronics wafers for susceptibility to stress-induced voiding. This method is valid for metallization/dielectric systems in which the dielectric is deposited onto the metallization at a temperature considerably above the intended use temperature, and above or equal to the deposition temperature of the metal. Although this is a wafer test, it is not a fast (less than 5 minutes per probe) test. It is intended to be used for lifetime prediction and failure analysis, not for production Go-NoGo lot checking. Committee(s):JC-14.2 Free download.Registrationorloginrequired. |
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GDDR5 MEASUREMENT PROCEDURES |
JEP171 | Aug 2014 |
This publication is to inform all industry participants of a unified procedure to enable consistent measurement across the industry. This document contains the measurement procedures for testing GDDR5. Committee(s):JC-42.3 Free download.Registrationorloginrequired. |
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Guidelines for Supplier Performance Rating |
JEP146B | May 2023 |
This publication establishes guidelines and provides examples by which customers can measure their suppliers based on mutually agreed upon objective criteria. Free download.Registrationorloginrequired. |
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JEDEC REQUIREMENTS FOR CLASS B MICROCIRCUITSStatus: Rescinded, May 2006 |
JEP101-C | Nov 1995 |
Committee(s):JC-13.2 Free download.Registrationorloginrequired. |
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SYMBOL AND LABELS FOR MOISTURE-SENSITIVE DEVICES - SUPERSEDED BY J-STD-033, April 2018.Status: Rescinded, November 2018 |
JEP113B | May 1999 |
Certain PSMC (Plastic Surface-mount Components) are subject to permanent damage due to moisture-induced failures encountered during high-temperature surface-mount processing unless appropriate precautions are observed. The purpose of this publication is to provide a distinctive symbol and labels to be used to identify those devices that require special packing and handling precautions. Committee(s):JC-14.1 Free download.Registrationorloginrequired. |
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INDEX OF TERMS DEFINED IN JEDEC PUBLICATIONS:Status: RescindedSeptember 2007 |
JEP120A | May 2000 |
This publication provides an index to terms that are defined in certain JEDEC publications. It is intended to promote the uniform use of these terms and their definitions while reducing the proliferation of new definitions for old terms. Committee(s):JC-10 |
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Guidelines for Particle Impact Noise Detection (PIND) Testing, Operator Training, and Certification |
JEP114A | May 2023 |
This publication is a guideline to test facilities in their efforts to establish and maintain consistent particle impact noise detection (PIND) testing. Free download.Registrationorloginrequired. |
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PROCEDURE FOR THE EVALUATION OF LOW-k/METAL INTER/INTRA-LEVEL DIELECTRIC INTEGRITY |
JEP159A | Jul 2015 |
This document is intended for use in the semiconductor IC manufacturing industry and provides reliability characterization techniques for low-k inter/intra level dielectrics (ILD) for the evaluation and control of ILD processes. It describes procedures developed for estimating the general integrity of back end-of-line (BEOL) ILD. Two basic test procedures are described, the Voltage-Ramp Dielectric Breakdown (VRDB) test, and the Constant Voltage Time-Dependent Dielectric Breakdown stress (CVS). Each test is designed for different reliability and process evaluation purposes. This document also describes robust techniques to detect breakdown and TDDB data analysis. Free download.Registrationorloginrequired. |
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BEADED THERMOCOUPLE TEMPERATURE MEASUREMENT OF SEMICONDUCTOR PACKAGESStatus: ReaffirmedJune 2006, September 2011, January 2015 |
JEP140 | Jun 2002 |
顾串珠热电偶温度测量ideline provides a procedure to accurately and consistently measure the temperature of semiconductor packages during exposure to thermal excursions. The guideline applications can include, but not limited to, temperature profile measurement in reliability test chambers and solder reflow operations that are associated with component assembly to printed wiring boards. Free download.Registrationorloginrequired. |
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SELECTION OF BURN-IN / LIFE TEST CONDITIONS AND CRITICAL PARAMETERS FOR QML MICROCIRCUITS |
JEP163A | Jan 2023 |
This publication is a guideline to assist manufacturers of integrated circuits in defining conditions for burn-in and life test of their products to meet quality and reliability performance requirements of MIL-PRF-38535. Free download.Registrationorloginrequired. |
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Test Procedure for the Measurement of Terrestrial Cosmic Ray Induced Destructive Effects in Power Semiconductor Devices |
JEP151A | Jan 2022 |
This test method defines the requirements and procedures for terrestrial destructive* single-event effects (SEE) for example, single-event breakdown (SEB), single-event latch-up (SEL) and single-event gate rupture (SEGR) testing . It is valid when using an accelerator, generating a nucleon beam of either; 1) Mono-energetic protons or mono-energetic neutrons of at least 150 MeV energy, or 2) Neutrons from a spallation spectrum with maximum energy of at least 150 MeV. This test method does not apply to testing that uses beams with particles heavier than protons. *This test method addresses a separate risk than does JESD89 tests for non-destructive SEE due to cosmic radiation effects on terrestrial applications. Committee(s):JC-14.1 Free download.Registrationorloginrequired. |