Global Standards for the Microelectronics Industry
Standards & Documents Search
Title | Document # | Date |
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STANDARD MANUFACTURERS IDENTIFICATION CODENOTE: JEP106U was in error starting with bank two an additional continuation code was added, JEP106U should be discarded. |
JEP106BF | Oct 2022 |
The manufacturers identification code is defined by one or more 8 bit fields, each consisting of 7 data bits plus 1 odd parity bit. The manufacturers identification code is assigned, maintained and updated by the JEDEC Office. The intent of this identification code is that it may be used whenever a digital field is required, e.g., hardware, software, documentation, etc. To make a request for an ID Code please go to//www.ljosalfur.com/Home/MIDCODE_request.cfm Free download.Registrationorloginrequired. |
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SPD General Standard. |
SPD4.1.2 | Jul 2008 |
Release No. 19. Item 2065.26 Committee(s):JC-45 Free download.Registrationorloginrequired. |
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SERIAL FLASH DISCOVERABLE PARAMETERS (SFDP)This document replaces JESD216F.01, Editorial changes to this document were approved by the TG, June 2022 |
JESD216F.02 | Jun 2022 |
The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the functional and feature capabilities of serial flash devices in a standard set of internal parameter tables. These parameter tables can be interrogated by host system software to enable adjustments needed to accommodate divergent features from multiple vendors. Any company may request a Function Specific ID by making a request to the JEDEC office atjuliec@jedec.org. Please include “Function Specific ID Request, JESD216” in the email subject line. Item 1775.73. Editorial changes listed in Annex, from original publication of JESD216F (December 2021). Committee(s):JC-42.4 Free download.Registrationorloginrequired. |
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UNIVERSAL FLASH STORAGE HOST CONTROLLER INTERFACE (UFSHCI), Version 3.0Status: SupersededAugust 2022 by JESD223E |
JESD223D | Jan 2018 |
This document has been superseded by JESD223E, however it is available for reference only. Committee(s):JC-64.1 Available for purchase:$141.00 Add to Cart Paying JEDEC Members mayloginfor free access. |
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UNIVERSAL FLASH STORAGE HOST CONTROLLER INTERFACE (UFSHCI), Version 2.1Status: Supersededby JESD223D, January 2018 |
JESD223C | Mar 2016 |
This document has been superseded by JESD223D, January 2018, however is available for reference only. Committee(s):JC-64.1 Free download.Registrationorloginrequired. |
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SPD Annex F, Address Multiplexed ROM |
SPD4.1.2.6 | Jun 1998 |
Release No.8 Committee(s):JC-42 Free download.Registrationorloginrequired. |
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SPD Annex C, Fast Page and Extended Data Out RAM |
SPD4.1.2.3 | Jan 1998 |
Release No.8 Committee(s):JC-42 Free download.Registrationorloginrequired. |
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Universal Flash Storage Host Controller Interface (UFSHCI), Version 4.0 |
JESD223E | Aug 2022 |
This standard describes a functional specification of the Host Controller Interface (HCI) for Universal Flash Storage (UFS). The objective of UFSHCI is to provide a uniform interface method of accessing the UFS hardware capabilities so that a standard/common Driver can be provided for the Host Controller. The common Driver would work with UFS host controller from any vendor. This standard includes a description of the hardware/software interface between system software and the host controller hardware. It is intended for hardware designers, system builders and software developers. This standard is a companion document to [UFS], Universal Flash Storage (UFS). The reader is assumed to be familiar with [UFS], [MIPI-UNIPRO], and [MIPI-M-PHY]. Item 206.25 Committee(s):JC-64.1 Available for purchase:$163.00 Add to Cart Paying JEDEC Members mayloginfor free access. |
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DDR5 Serial Presence Detect (SPD) Contents Version 1.1Release Number: Version 1.1 |
JESD400-5A | Sep 2022 |
This standard describes the serial presence detect (SPD) values for all DDR5 memory modules. In this context, “modules” applies to memory modules like traditional Dual In-line Memory Modules (DIMMs) or solder-down motherboard applications. The SPD data provides critical information about all modules on the memory channel and is intended to be used by the system's BIOS in order to properly initialize and optimize the system memory channels. Committee(s):JC-45 Free download.Registrationorloginrequired. |
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UNIVERSAL FLASH STORAGE, Version 4.0 |
JESD220F | Aug 2022 |
然而,这个文件替换所有过去的版本JESD220E, January 2020 (V 3.1), is available for reference only. This standard specifies the characteristics of the UFS electrical interface and the memory device. Such characteristics include (among others) low power consumption, high data throughput, low electromagnetic interference and optimization for mass memory subsystem efficiency. The UFS electrical interface is based on an advanced differential interface by MIPI M-PHY specification which together with the MIPI UniPro specification forms the interconnect of the UFS interface. Committee(s):JC-64.1 Available for purchase:$369.00 Add to Cart Paying JEDEC Members mayloginfor free access. |
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RADIO FRONT END - BASEBAND (RF-BB) INTERFACE |
JESD96A | Feb 2006 |
The normative information in this standard is intended to provide a technical design team to construct the interface on a FED and a BED such that they will operate correctly with each other (at the interface level), when designed to this specification. Additional informative information is provided in the appendices to help illustrate the normative material. This document addresses the following interface topics: 1) RF-BB Electrical layer: time and amplitude specifications for lines, drivers, receivers, clocks; 2)RF-BB Link layer: bits, clock-data synchronization, power modes; 3) RF-BB Transport layer: data types, data framing, data bandwidth, connection to core IC; 4) RF-BB Interface Registers This document defines a high-speed serial link that enables the bi-directional transfer of data and control information between the FED and BED. The document does not mandate the use of specific signaling, standard framing or standard messaging needed to make this an interoperable interface standard for RF devices or BB devices. Committee(s):JC-61 Free download.Registrationorloginrequired. |
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UNIVERSAL FLASH STORAGE (UFS), Version 3.0Status: SupersededJanuary 2020 |
JESD220D | Jan 2018 |
This document has been superseded by JESD220E, January 2020, however is available for reference only. Patents(): A complete list of Assurance/Disclosure Forms is available to JEDEC members in the Members Area. Non-members can obtain individual Assurance/Disclosure Forms on request from the JEDEC office. Committee(s):JC-64.1 Available for purchase:$355.00 Add to Cart Paying JEDEC Members mayloginfor free access. |
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UNIVERSAL FLASH STORAGE (UFS), Version 3.1 |
JESD220E | Jan 2020 |
This document has been superseded by JESD220F, August 2022, however is available for reference only. Patents(): A complete list of Assurance/Disclosure Forms is available to JEDEC members in the Members Area. Non-members can obtain individual Assurance/Disclosure Forms on request from the JEDEC office. Committee(s):JC-64.1 Available for purchase:$355.00 Add to Cart Paying JEDEC Members mayloginfor free access. |
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SPD Annex J: Serial Presence Detect for DDR2 SDRAM |
SPD4.1.2.10 | Jan 2007 |
Release No. 17 Free download.Registrationorloginrequired. |
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Addendum No. 1 to JESD96A - INTEROPERABILITY AND COMPLIANCE TECHNICAL REQUIREMENTS FOR JEDEC STANDARD JESD96A - RECOMMENDED PRACTICE FOR USE WITH IEEE 802.11N |
JESD96A-1 | Jan 2007 |
The normative information in this publication is intended to provide a technical design team to construct the interface on a FED and a BED such that they will operate correctly with each other (at the interface level), when designed to JESD96A. Committee(s):JC-61 Free download.Registrationorloginrequired. |
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EMBEDDED MULTI-MEDIA CARD (e•MMC), ELECTRICAL STANDARD (5.1) |
JESD84-B51A | Jan 2019 |
This document provides a comprehensive definition of thee•MMC Electrical Interface, its environment, and handling. It also provides design guidelines and defines a tool box of macro functions and algorithms intended to reduce design-in overhead. The purpose of this standard is the definition of thee•MMC Electrical Interface, its environment and handling. It provides guidelines for systems designers. Item 67.14. 然而,这个文件替换所有过去的版本links to the replaced versions are provided here for reference only:JESD84-B51, February 2015;JESD84-B50.1, July 2014 (Editorial revision of JESD84-B50);JESD84-B50, September 2013 (Revision of JESD84-B451);JESD84-B451, June 2012 (Revision of JESD84-B45, June 2011) Patents(): A complete list of Assurance/Disclosure Forms is available to JEDEC members in the Members Area. Non-members can obtain individual Assurance/Disclosure Forms on request from the JEDEC office. Committee(s):JC-64 Available for purchase:$327.00 Add to Cart Paying JEDEC Members mayloginfor free access. |
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UNIVERSAL FLASH STORAGE, UFS 2.2 |
JESD220C-2.2 | Aug 2020 |
The purpose of this standard is definition of a UFS Universal Flash Storage electrical interface and a UFS memory device. This standard defines a unique UFS feature set and includes the feature set of eMMC standard as a subset. This standard replaces JESD220C, UFS 2.1, and introduces a feature called WriteBooster. Item 138.88. Committee(s):JC-64.1 Free download.Registrationorloginrequired. |
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SPD Annex D, DDR Synchronous DRAM (DDR SDRAM) |
SPD4.1.2.4 | Jan 2004 |
Release No.13 Free download.Registrationorloginrequired. |
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240-Pin PC2-5300/PC2-6400 DDR2 SDRAM Unbuffered DIMM Design Specification |
MODULE4.20.13 | May 2021 |
Release 31. Item 2167.05This revision contains terminology updates only. Committee(s):JC-45,JC-45.2,JC-45.3 Free download.Registrationorloginrequired. |
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Universal Flash Storage (UFS), Version 2.1Status: SupersededAugust 2020 |
JESD220C-2.1 | Mar 2016 |
This document has been superseded by JESD220C-2.2, August 2020, and is provided here for reference purposes only. This standard specifies the characteristics of the UFS electrical interface and the memory device. Suchcharacteristicsinclude(amongothers)lowpowerconsumption,highdatathroughput,lowelectromagnetic interference and optimization for mass memory subsystem efficiency. The UFS electricalinterface is based on an advanced differential interface by MIPI M-PHY specification which together withthe MIPI UniPro specification forms the interconnect of the UFS interface. The architectural model isreferencing the INCITS T10 (SCSI) SAM standard and the command protocol is based on INCITS T10(SCSI) SPC and SBC standards.Item 133.00B Committee(s):JC-64.1 Free download.Registrationorloginrequired. |