Global Standards for the Microelectronics Industry
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Title | Document # | Date |
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多片包(MCP)和离散e•MMC, e•2毫米C, and UFSRelease Number: 32 |
MCP3.12.1 | Mar 2023 |
Item 140.07B. This section provides electrical interface items related to Multi-Chip Packages (MCP) and Stacked-Chip Scale Packages (SCSP) of mixed memory technologies including Flash (NOR and NAND), SRAM, PSRAM, LPDRAM, USF, etc. These items include die-on-die stacking within a single encapsulated package, package-on-package or module-in-package technologies, etc. The Section also contains Silicon Pad Sequence information for the various memory technologies to aid in the design and electrical optimization of the memory sub-system or complete memory stacked solution. Committee(s):JC-64.2 Free download.Registrationorloginrequired. |