Global Standards for the Microelectronics Industry
JEDEC Committee:
JC-40.1 Digital Logic Families and Applications
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Recent Documents
TS511X, TS521X Serial Bus Thermal Sensor Device Standard | JESD302-1A | Aug 2023 |
SPD5118 HUB and SERIAL PRESENCE DETECT DEVICE STANDARD | JESD300-5B.01 | May 2023 |
PMIC50x0 Power Management IC Standard | JESD301-1A.02 Rev. 1.8.5 | Apr 2023 |
PMIC5100 POWER MANAGEMENT IC STANDARD, Rev 1.03 | JESD301-2 | Oct 2022 |
PSO-N/PQFN PINOUTS STANDARDIZED FOR 14-, 16-, 20-, AND 24-LEAD LOGIC FUNCTIONS: | JESD75-6 | Mar 2006 |
STANDARD TEST LOADS FOR DUAL-SUPPLY LEVEL TRANSLATION DEVICES | JESD203 | Nov 2005 |
SON/QFN PACKAGE PINOUTS STANDARDIZED FOR 1-, 2-, AND 3-BIT LOGIC FUNCTIONS | JESD75-5 | Jul 2004 |
STANDARD DESCRIPTION OF 1.5 V CMOS LOGIC DEVICES: | JESD76-3 | Aug 2001 |
DESCRIPTION OF 1.8 V CMOS LOGIC DEVICES: | JESD76 | Apr 2000 |
DIGITAL BIPOLAR LOGIC PINOUTS FOR CHIP CARRIERS: | JESD2 | Dec 1982 |