Global Standards for the Microelectronics Industry
Standards & Documents Search
Title | Document # | Date |
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DDR2 DIMM CLOCK SKEW MEASUREMENT PROCEDURE USING A CLOCK REFERENCE BOARD |
JEP152 | May 2007 |
This document is the work product of the JC-45.1 DDR2 DIMM Clock Skew Measurement task group.The purpose of this document is to define procedures to measure clock parameters on registered DIMMs using the DDR2 Clock Reference Board. It is NOT the intent of this document to set specification values or validation requirements. Free download.Registrationorloginrequired. |
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High Speed DDR SRAM in 165 BGA |
SRAM3.7.10 | Feb 2008 |
Release No. 17. Item 1755 Free download.Registrationorloginrequired. |
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SRAM Introduction |
SRAM3.7 | Oct 2001 |
Release No. 11 Committee(s):JC-42.2 Free download.Registrationorloginrequired. |
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Bit Wide TTL SRAM |
SRAM3.7.1 | Dec 1995 |
Release No. 5 Free download.Registrationorloginrequired. |
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Nibble Wide ECL SRAM |
SRAM3.7.4 | Dec 1994 |
Release No.04 Committee(s):JC-42 Free download.Registrationorloginrequired. |
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Byte Wide SRAM |
SRAM3.7.5 | Apr 2003 |
Release No.12 Free download.Registrationorloginrequired. |
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64 & 72 Pin ZIP/SIMM SRAM Module |
MODULE4.4.1 | Jun 1997 |
Release No.9 Free download.Registrationorloginrequired. |
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Eight Byte Wide (X64/72) MOS SRAM |
SRAM3.7.9 | Jun 2007 |
Release No. 16A. Item 1480.05 and 1531.04 Free download.Registrationorloginrequired. |
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Word Wide TTL and MOS SRAM |
SRAM3.7.7 | Apr 2007 |
Release No. 16. Item 1541.03 Free download.Registrationorloginrequired. |
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Double Word Wide MOS SRAM |
SRAM3.7.8 | Apr 2007 |
Release No. 16. Item 1541.03 Free download.Registrationorloginrequired. |
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BUS INTERCONNECT LOGIC (BIC) FOR 1.2 V |
JESD8-16A | Nov 2004 |
This standard defines the electrical parameters for high-speed interfaces for use in the 1.2V electrical environment. Included in the standard are a single ended signaling interface suitable for parallel buses, and a differential signaling interface suitable for clock applications or parallel differential buses. JEDEC BIC Standard JESD8-16A continues the tradition of the JESD8-xx standards, defining electrical interfaces for the industry as new technologies and bus requirements develop. Previously, JEDEC defined standard JESD8-6, the HSTL standard, for use in 1.5V electrical environments. BIC is similar to HSTL, except the power supply voltage has dropped from 1.5V to 1.2V, and interface requirements are tightened to allow much higher speeds Committee(s):JC-16 Free download.Registrationorloginrequired. |
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POD12 ‐ 1.2 V PSEUDO OPEN DRAIN INTERFACE |
JESD8-24 | Aug 2011 |
This document defines the 1.2 V Pseudo Open Drain Interface family of interface standards, POD12, which are generally expected to be implemented with differential amp-based input buffers that, when in single-ended mode, employ an externally supplied (or internal supplied) reference voltage controlled trip-point. Committee(s):JC-16 Free download.Registrationorloginrequired. |
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POD10-1.0 V PSUEDO OPEN DRAIN INTERFACE |
JESD8-25 | Sep 2011 |
This document defines the 1.0 V Pseudo Open Drain Interface family of interface standards, POD10, which are generally expected to be implemented with differential amp-based input buffers that, when in single-ended mode, employ an externally supplied (or internal supplied) reference voltage controlled trip-point. Committee(s):JC-16 Free download.Registrationorloginrequired. |