Global Standards for the Microelectronics Industry
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Displaying 1 - 3 of 3 documents.
Title | Document # | 日期 |
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RESISTANCE TO SOLDER SHOCK FOR THROUGH-HOLE MOUNTED DEVICESStatus: Reaffirmed菲bruary 2023 |
JESD22-B106E | Nov 2016 |
This test method is used to determine whether solid state devices can withstand the effect of the temperature shock to which they will be subjected during soldering of their leads in a solderwave process and/or solder fountain (rework/replacement) process. The heat is conducted through the leads into the device package from solder heat at the reverse side of the board. Committee(s):JC-14.1 Free download.Registrationorloginrequired. |
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GUIDELINE FOR CHARACTERIZING SOLDER BUMP ELECTROMIGRATION UNDER CONSTANT CURRENT AND TEMPERATURE STRESSStatus: ReaffirmedJune 2011 |
JEP154 | Jan 2008 |
This document describes a method to test the electromigration (EM) susceptibility of solder bumps, including other types of bumps, such as solder capped copper pillars, used in flip-chip packages. The method is valid for Sn/Pb eutectic, high Pb, and Pb-free solder bumps. The document discusses the advantages and concerns associated with EM testing, as well as options for data analysis. Free download.Registrationorloginrequired. |
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MARKING, SYMBOLS, AND LABELS OF LEADED AND LEAD-FREE TERMINAL FINISHED MATERIALS USED IN ELECTRONIC ASSEMBLY |
J-STD-609B | Apr 2016 |
This standard applies to components and assemblies that contain Pb-free and Pb-containing solders and finishes. This standard describes the marking of components and the labeling of their shipping containers to identify their 2nd level terminal finish or material, and applies to components that are intended to be attached to boards or assemblies with solder or mechanical clamping or are press fit. This standard also applies to 2nd level terminal materials for bumped die that are used for direct board attach. Free download.Registrationorloginrequired. |