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JEDEC Publishes Major Update to JEP30 PartModel Guidelines

Emilyd — Wednesday, May 24, 2023

ARLINGTON, VA., USA – May 24, 2023 – JEDEC Solid State Technology Association, the global leader in the development of standards for the microelectronics industry, today announced significant updates to the JEP30 PartModel Guidelines, including all reference documents and related XML Schema files. JEP30 and its constituent documents are available for free download from the JEDEC website.

PART MODEL SCHEMAS

Emilyd — Thursday, March 09, 2023

This download includes all files under the parent schema JEP30-10v2-0-0 (Committees: JC-11, JC-11.2) including:

Part Model Electrical Guidelines for Electronic-Device Packages – XML Requirements

10061783 — Thursday, March 09, 2023

这斯坦dard establishes the requirements for exchanging part data between part manufacturers and their customers for electrical and electronic products. This standard applies to all forms of electronic parts. It forms part of the Part Model XML Schema, which covers the parental structure for the electrical, physical, Electrical, assembly process classification data along with materials and substances that may be present in the supplied product or subproducts. This Guideline specifically focuses on the “Electrical” sub-section of the Part Model.

JEDEC to Host In-Person Memory Forum and DDR5 Workshop

Emilyd — Thursday, April 21, 2022

< >强阿灵顿,弗吉尼亚州美国——2022年4月21日– JEDEC Solid State Technology Association, the global leader in the development of standards for the microelectronics industry, today announced that it is hosting a Server/Cloud Computing/Edge Forum, a Memory Tutorial introductory class, and an in-depth, two-day technical workshop focused its DDR5 standard in Santa Clara, CA from May 23-26, 2022. Space is limited and for best rates, register now on the JEDEC website.

1.05 V CMOS

juliec — Wednesday, April 29, 2020

这斯坦dard defines the input, output specifications and ac test conditions for devices that are designed to operate narrow range 1.05 V CMOS level. Item 159.01

0.5 V LOW VOLTAGE SWING TERMINATED LOGIC (LVSTL05)

juliec — Wednesday, June 12, 2019

这斯坦dard defines power supply voltage range, dc interface, switching parameter and overshoot/undershoot for high speed low voltage swing terminated NMOS driver family digital circuits. The specifications in this standard represent a minimum set of interface specifications for low voltage terminated circuits. Item 159.03

1.8 V HIGH-SPEED LVCMOS (HS_LVCMOS) INTERFACE

juliec — Monday, April 09, 2018

这斯坦dard defines the dc and ac input levels, output levels, and input overshoot and undershoot specifications for the 1.8 V High-speed LVCMOS (HS_LVCMOS) interface. The non-terminated interface has a switching range that is nominally expected to be 0 V to 1.8 V.

JEP30: PartModel Guidelines

Emilyd — Monday, April 09, 2018

JEP30 and its related documents are currently published and maintained as a JEDEC-wide project between the JC-11, JC-14, JC-15 and JC-16 Committees. JEP30 establishes the requirements for exchanging part data between part manufacturers and their customers for electrical and electronic products. As one example, the standard could be used to define a part in sufficient detail to enable process efficiencies during the part and product life cycles, i.e., design, purchasing, manufacturing, quality control, test, material deceleration, supply chain, etc.

POD125 - 1.25 V PSEUDO OPEN DRAIN I/O

juliec — Thursday, September 21, 2017

Editorial Terminology Update. This standard defines the DC and AC single-ended (data) and differential (clock) operating conditions, I/O impedances, and the termination and calibration scheme for 1.25 V Pseudo Open Drain I/Os. The 1.25 V Pseudo Open Drain interface, also known as POD125, is primarily used to communicate with GDDR6 SGRAM devices.

0.6 V LOW VOLTAGE SWING TERMINATED LOGIC (LVSTL06)

juliec — Wednesday, December 21, 2016

这斯坦dard defines power supply voltage range, dc interface, switching parameter and overshoot/undershoot for high speed low voltage swing terminated NMOS driver family digital circuits with 0.6V supply. The specifications in this standard represent a minimum set of interface specifications for low voltage terminated circuits. Item 180.24.

MULTI-WIRE MULTI-LEVEL I/O STANDARD

juliec — Wednesday, June 29, 2016

这斯坦dard defines the DC and AC operating conditions, I/O impedances, termination characteristics, and compliance test methods of I/O drivers and receivers used in multi-wire, multi-level signaling interfaces. The multi-wire interfaces defined by this specification all utilize quaternary signal levels. Item 153.00

300 mV INTERFACE

juliec — Tuesday, July 07, 2015

这个标准是定义和接口CMOS rail to rail signal that uses a 300 mV signal swing. This specification defines the maximum signaling rate, the signal
levels, overshoot and undershoot limits, and the maximum input capacitance. This interface is useful in short distance applications, typically of less than 5 mm.

1.2 V HIGH-SPEED LVCMOS (HS_LVCMOS) INTERFACE

juliec — Thursday, September 29, 2011

这斯坦dard defines the dc and ac input levels, output levels, and input overshoot and undershoot specifications for the 1.2 V High-speed LVCMOS (HS_LVCMOS) interface. The non-terminated interface has a switching range that is nominally expected to be 0 V to 1.2 V and is primarily intended to support communications with Wide I/O SDRAM devices.

POD10-1.0 V PSUEDO OPEN DRAIN INTERFACE

juliec — Wednesday, September 14, 2011

This document defines the 1.0 V Pseudo Open Drain Interface family of interface standards, POD10, which are generally expected to be implemented with differential amp-based input buffers that, when in single-ended mode, employ an externally supplied (or internal supplied) reference voltage controlled trip-point.

POD12 ‐ 1.2 V PSEUDO OPEN DRAIN INTERFACE

juliec — Tuesday, August 23, 2011

This document defines the 1.2 V Pseudo Open Drain Interface family of interface standards, POD12, which are generally expected to be implemented with differential amp-based input buffers that, when in single-ended mode, employ an externally supplied (or internal supplied) reference voltage controlled trip-point.
Although this standard is named for the nominal value of VDDQ to be used, it is the input trip-point value that provides for inter operability of POD12 compliant devices.

POD135 - 1.35 V PSEUDO OPEN DRAIN I/O

juliec — Monday, July 19, 2010

Editorial, Terminology Update. This standard defines the dc and ac single-ended (data) and differential (clock) operating conditions, I/O impedance's, and the termination and calibration scheme for 1.35 V Pseudo Open Drain I/Os. The 1.35 V Pseudo Open Drain interface, also known as POD135, is primarily used to communicate with GDDR5 or GDDR5M SGRAM devices. Item 146.01B

UNIFIED WIDE POWER SUPPLY VOLTAGE RANGE CMOS DC INTERFACE STANDARD FOR NON-TERMINATED DIGITAL INTEGRATED CIRCUITS

Emilyd — Wednesday, January 27, 2010

这斯坦dard defines DC interface parameters and test conditions for a family of non-terminated CMOS digital circuits intended for use over a wide power supply voltage range. The standard bridges a number of existing JEDEC standards in the JESD8-x family to facilitate applications that operate over an ultra-wide power supply voltage range in order to achieve lower power dissipation or higher performance.

BUS INTERCONNECT LOGIC (BIC) FOR 1.2 V

admin — Wednesday, September 30, 2009

这斯坦dard defines the electrical parameters for high-speed interfaces for use in the 1.2V electrical environment. Included in the standard are a single ended signaling interface suitable for parallel buses, and a differential signaling interface suitable for clock applications or parallel differential buses. JEDEC BIC Standard JESD8-16A continues the tradition of the JESD8-xx standards, defining electrical interfaces for the industry as new technologies and bus requirements develop.

HSUL_12 LPDDR2 AND LPDDR3 I/O WITH OPTIONAL ODT

admin — Friday, August 28, 2009

这斯坦dard defines the input, output specifications and ac test conditions for devices that are designed to operate in the High Speed Unterminated Logic (HSUL_12) logic switching range, nominally 0 V to 1.2 V. The standard may be applied to ICs operating with separate VDD and VDDQ supply voltages.

POD15 - 1.5 V PSEUDO OPEN DRAIN I/O

admin — Wednesday, July 08, 2009

Terminology Update.This standard defines the dc and ac single-ended (data) and differential (clock) operating conditions, I/O impedance, and the termination and calibration scheme for 1.5 V Pseudo Open Drain I/Os. The 1.5 V Pseudo Open Drain interface, also known as POD15, is primarily used to communicate with GDDR4 and GDDR5 SGRAM devices. Item 135.01